1. Field of the Invention
The invention relates to the field of microprocessors and more particularly to the control of read/write cycles.
2. Prior Art
It is not uncommon for a microprocessor to include a write buffer. A write buffer accepts data from a central processing unit (CPU) over an internal bus of the microprocessor and temporarily stores the data before it is written into external memory over an external bus. These buffers are used to increase the performance of microprocessors by accepting data at a faster rate than the data can be written into external memory. Without such buffers, the CPU would be forced to operate at the typically slower rate of external RAM (such as dynamic RAMs) for write cycles. Moreover, external memory is not always immediately available, for instance, it may be refreshing when access is requested by the CPU.
In some cases the CPU requests a read cycle before all the data in the write buffer has been written into external memory. (Read cycles must be intermixed with write cycles if CPU performance is to be maximized.) But what if the CPU is addressing a location in external memory for which data is stored in the write buffer? If the read cycle is allowed to proceed, the old data will be read into the CPU while the new data remains uselessly in the write buffer. This, of course, presents an unacceptable condition.
One method of preventing the reading of the old data by the CPU is simply to prevent read cycles until all the data in the write buffers has been read into external memory. The disadvantage of this method is that it impacts the performance of the microprocessor since the microprocessor must wait a potentially long time to allow the write buffer to update external memory before a read cycle.
Another method of avoiding this problem is to compare the addresses generated for the read cycle against the addresses associated with the data in the write buffer. (The write buffer typically stores an address and the data to be stored at that address.) If there is no match, a read cycle can occur since the CPU is not seeking data stored in the write buffer. This method has the disadvantage of requiring a significant amount of logic to perform the comparison of the addresses.
It is also known in the prior art to use cache memories in connection with microprocessors. Some of these cache memories are "write-through" cache memories in that data generated by the CPU updates the cache memory if the address associated with the data is found in the cache memory in addition to being written into external memory.
As will be seen, the present invention provides a method and apparatus for reordering read/write cycles in a microprocessor that includes a write buffer and a cache memory. The invention is realized with a minimum of circuitry.